1. Field of the Invention
The present invention relates to dynamic random access memories (DRAMs), and, more particularly, to a structure and process for achieving high density DRAMs.
2. Description of the Related Art
A one-transistor dynamic memory cell comprises a pass-gate, storage capacitor and electrical connections to a bit-line, word-line and capacitor plate. The pass-gate is used to access the capacitor for reading and writing the memory cell.
The cell stores the value of a bit (one or zero) by the presence or absence of charge on the storage capacitor. The capacitor typically comprises (1) a polysilicon capacitor plate, (2) an inversion region on the semiconductor (e.g., silicon) surface under the capacitor plate, and (3) a dielectric (e.g., silicon dioxide) separating the capacitor plate and the inversion region.
In conventional one-transistor dynamic memory cells, the polysilicon capacitor plate is common to all memory cells in the device. A potential is applied to the capacitor plate sufficient to generate the inversion region in the capacitor areas. The inversion region in each memory cell is isolated from adjacent cells by the level of impurity doping in the silicon separating the cells and by field oxide underneath the capacitor plate.
Recent advances in the art of DRAMs have been directed to decreasing the size of the memory cell, in order to provide a higher packing density of cells, with concomitant increase in device operating speed. In one such development, the capacitor is formed by a trench to minimize the surface area required for the capacitor, yet provide the same capacitance (about 50 fF).
Such a cell, appropriately termed the Trench Capacitor cell (Corrugated Capacitor cell) was first proposed for megabit dynamic random access memories by Sunami et al, "A Corrugated Capacitor Cell for Megabit Dynamic MOS Memories", 1982 IEDM Technical Digest, pp. 806-808 (1982). At greater than 1 Megabit integration levels, where the feature size ranges from about 0.8 to 1 .mu.m, leakage current between adjacent trench capacitors becomes a limiting factor for data retention.
In conventional approaches, lightly doped P.sup.- epitaxial substrates are used as starting material for N-well (or twin-well) CMOS processes in the periphery support circuitry. In order to suppress leakage, heavy core implants are used to obtain a P-well concentration of greater than 1.times.10.sup.16 cm.sup.-3, as described by Elahy et al, "Trench Capacitor Leakage in Mbit DRAMs", 1984 IEDM Technical Digest, pp. 248-251 (1984).
However, for 5 .mu.m or deeper trenches, it is impractical to achieve this concentration uniformly over the entire trench depth by using a surface implant and drive. This sets up a restriction on achievable trench depth.
One method which solves the leakage problem incorporates a Substrate Plate Cell concept, as described by Sakamoto et al, "Buried Storage Electrode (BSE) Cell for Megabit DRAMs", 1985 IEDM Technical Digest, pp. 710-713, (1985) and Lu et al, "The SPT Cell--A New Substrate-Plate Trench Cell for DRAMs", 1985 IEDM Technical Digest, pp. 771-772 (1985). In this method, the storage node is the polysilicon (poly) plug inside the trench.
It is also conceivable to use boron side-wall doping to reduce punch-through between trenches. However, this is a complex process, and is not widely used in the industry.
As the memory cell above is shrunk to a smaller size, the trench capacitor storing the data must occupy less chip area but retain the same storage capacitance (.apprxeq.50 fF). Thus, what is needed is a new scheme that allows for smaller, deeper and more closely spaced trench capacitors.